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Sheet目录3871

43页 44页 45页 46页 [47页]48页 49页 50页 51页

PIC18F/LF1XK50

DS41350E-page 140

Preliminary

2010 Microchip Technology Inc.

15.2.1

REGISTERS

The MSSP module has four registers for SPI mode

operation. These are:

SSPCON1 – Control Register

SSPSTAT – STATUS register

SSPBUF – Serial Receive/Transmit Buffer

SSPSR – Shift Register (Not directly accessible)

SSPCON1 and SSPSTAT are the control and STATUS

registers in SPI mode operation. The SSPCON1 regis-

ter is readable and writable. The lower 6 bits of the

SSPSTAT are read-only. The upper two bits of the

SSPSTAT are read/write.

SSPSR is the shift register used for shifting data in and

out. SSPBUF provides indirect access to the SSPSR

bytes are written, and from which data bytes are read.

In receive operations, SSPSR and SSPBUF together

create a double-buffered receiver. When SSPSR

receives a complete byte, it is transferred to SSPBUF

and the SSPIF interrupt is set.

During

transmission,

the

SSPBUF

not

double-buffered. A write to SSPBUF will write to both

SSPBUF and SSPSR.

REGISTER 15-1:

SSPSTAT: MSSP STATUS REGISTER (SPI MODE)

R/W-0

R-0

SMP

CKE

D/A

R/W

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

SMP: Sample bit

SPI Master mode:

= Input data sampled at end of data output time

= Input data sampled at middle of data output time

SPI Slave mode:

SMP must be cleared when SPI is used in Slave mode.

bit 6

CKE: SPI Clock Select bit(1)

= Transmit occurs on transition from active to Idle clock state

= Transmit occurs on transition from Idle to active clock state

bit 5

D/A: Data/Address bit

Used in I2C mode only.

bit 4

P: Stop bit

Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.

bit 3

S: Start bit

Used in I2C mode only.

bit 2

R/W: Read/Write Information bit

Used in I2C mode only.

bit 1

UA: Update Address bit

Used in I2C mode only.

bit 0

BF: Buffer Full Status bit (Receive mode only)

= Receive complete, SSPBUF is full

= Receive not complete, SSPBUF is empty

Note 1:

Polarity of clock state is set by the CKP bit of the SSPCON1 register.

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